Read the operand: a value or an address?

By UK A Level Computer Science · independent study · myAudience

A fictional 12-bit instruction and immediate/direct addressing paths, followed by full accumulator and memory traces.

Image: illustration, not a documentary photograph. This original teaching machine uses a 5-bit opcode and a 7-bit unsigned operand in a 12-bit instruction. The shown word 00010 0001101 is decimal 269 or hexadecimal 0x10D and means LOAD direct 13 in this toy only. LOAD immediate 13 supplies the datum 13; LOAD direct 13 reads the word 40 from M[13]. Starting from ACC=0, M[13]=40 and M[14]=0, the direct-load/immediate-add program produces 43, while the immediate-load/direct-add program produces 53. Both store to cell 14 and preserve cell 13. The paths and state traces are conceptual, not a real processor layout or a universal instruction encoding. Unsigned operand width, unknown-opcode rejection and arithmetic range limits are explained in the full lesson. The 160-pixel preview supports recognition, not reading every bit or instruction. · Original project scientific illustration; defined teaching model, not a calibrated measurement or exam-board figure.

An operand field is not self-explanatory. Suppose its bits represent 13. That number might be the value a calculation needs, or it might identify a location holding the value. Confusing those interpretations can produce a program that executes successfully and computes the wrong answer. Immediate addressing uses the operand as the datum itself. Direct addressing uses the operand as an address. The specification allows that address to identify memory or a register; this lesson chooses the memory case explicitly. An instruction's operation and addressing mode determine the interpretation, rather than the appearance of the operand alone.

A processor instruction set supplies those meanings. There is no universal binary pattern for LOAD, and an assembly spelling is not a portable promise about every processor. Our original teaching machine has 12-bit unsigned words, a 12-bit accumulator called ACC and 128 word-addressed memory cells numbered 0 to 127. Each instruction word has a five-bit opcode followed by a seven-bit operand. The opcode meanings include the addressing mode: 00001 means LOAD immediate, 00010 LOAD direct, 00011 ADD immediate, 00100 ADD direct and 00101 STORE direct. Other opcode patterns are undefined in this toy and must be rejected rather than guessed. The written mnemonics describe this toy only.

Separate the capacity of a field from the meaning assigned to a pattern. Five bits provide 32 possible opcode patterns, but this machine defines only five of them. Seven bits provide 128 unsigned operand values, 0 through 127. A direct operand can therefore select any of the 128 cells. An immediate operand supplies only a seven-bit unsigned value, even though ACC can hold a 12-bit result between 0 and 4095. A 12-bit instruction has 4096 possible raw patterns; that does not make every pattern a valid instruction. The memory's ideal packed payload is 128 times 12, or 1536 bits, equivalent to 192 eight-bit bytes. This is a bit-capacity calculation, not a claim about physical allocation, padding or byte addressability.

Decode a word by respecting its field boundaries. The word 00010 0001101 divides into opcode 00010 and operand 0001101. The operand is 8+4+1=13, and the whole unsigned word is 2 times 128 plus 13, or 269, written 0x10D in hexadecimal. Because opcode 00010 means LOAD direct, execution reads M[13] and copies that word into ACC. It does not load 13 merely because 13 appears in the instruction. Conversely, 00001 0001101 means LOAD immediate and places 13 in ACC. Both words have the same operand bits; changing the opcode changes the interpretation.

A state trace makes those differences visible. Begin with ACC=0, M[13]=40 and M[14]=0. LOAD direct 13 copies 40 into ACC without altering either cell. ADD immediate 3 adds the datum 3 to the current accumulator, producing 43. STORE direct 14 then writes the accumulator's current word to M[14]. It leaves ACC=43 and M[13]=40. Reading a cell, replacing the accumulator and writing a cell are different transitions; recording only a final answer hides which one happened. In this example every arithmetic result is within the unsigned 12-bit range, so no overflow convention is required to justify the trace.

Now change the program while keeping the initial state. LOAD immediate 13 puts 13 in ACC. ADD direct 13 reads the word 40 from M[13] and adds it, giving 53. STORE direct 14 writes 53 to M[14]. In the first program, memory supplies the initial accumulator value and the addition uses an immediate datum. In the second, the initial value is immediate and memory supplies the addend. Neither program changes M[13], because neither stores to that address. Both replace M[14], and both leave the final accumulator equal to the stored result. The difference is a data-flow difference, not a difference in the number of instructions.

Test an explanation with a changed state and with an invalid instruction. If M[13] is 7 instead of 40, the first program ends at 7+3=10 and the second at 13+7=20. The immediate operand 13 stays 13 even when the contents of cell 13 change. A direct operand 13 keeps selecting that cell, so its retrieved value changes. An attempted operand 128 cannot be represented in seven bits: truncating it to zero would silently address a different cell and is not permitted. Likewise, opcode 11111 has no defined operation here. Reject it before a state mutation. Negative immediates, arithmetic overflow, flags, branches, instruction fetch sequencing and actual assembler diagnostics need separate policies and remain outside this model.

Actual current official A-level Computer Science architecture HTML, checked 6 October 2026, sections the related topic, the related topic and the related topic:. The current canonical source identifies specification version 1.6, 31 July 2023; no newer version is inferred from an HTML retrieval date. Formal association is the existing grouped requirement the related topic only. Instruction-set and assembly-operation sections provide context, not a claim that all their demands are delivered. Direct addresses may identify memory or registers in the official scope; this toy chooses word-addressed memory. All numbers, opcodes, questions and answers are original. Full architecture coverage, independent assessment and qualification closure remain open. The reviewed illustration is schematic; its full caption explains the toy instruction set and why small previews support recognition rather than detailed reading.

An address and the contents at that address belong to different levels of description. Write M[13]=40 to distinguish the location from its stored word, and trace every read and write explicitly. Direct addressing does not mean that the datum is physically adjacent to the instruction, while immediate addressing does not involve an additional memory read for the operand in this execution model. Instruction fetch itself is a separate process, so that last statement does not mean that a whole immediate instruction executes without any memory activity. This lesson develops the immediate/direct distinction, not a full processor architecture or an assessed qualification. The examples and trace questions are original; no publisher question or processor encoding is copied.

Worked example: For the toy machine defined above, begin with ACC=0, M[13]=40 and M[14]=0. Decode 00010 0001101, then execute LOAD direct 13; ADD immediate 3; STORE direct 14. Give the accumulator and both cells after each instruction. Explain why the first instruction does not load 13 and why the store does not change M[13]. Check the number of possible field patterns and the ideal packed memory payload.

1. Split the 12-bit word after five bits. Opcode 00010 has unsigned value 2 and means LOAD direct in this particular instruction set. Operand 0001101 has unsigned value 13. The whole word is 2×128+13=269=0x10D. The operation reads M[13]; it does not treat the address field as an immediate datum.

2. Initially the state is (ACC, M[13], M[14])=(0,40,0). LOAD direct 13 changes it to (40,40,0). The source cell is read, not cleared or overwritten.

3. ADD immediate 3 uses the datum 3, giving (43,40,0). The instruction does not read M[3]. No result exceeds 4095, and there is no need to assume a wraparound or saturation rule.

4. STORE direct 14 writes the current accumulator to the selected destination, giving (43,40,43). The destination is cell 14, so cell 13 is unchanged. ACC also remains 43 under the stated toy operation.

5. Five opcode bits permit 2⁵=32 patterns; seven operand bits permit 2⁷=128 values; twelve instruction bits permit 2¹²=4096 raw patterns. Only five opcode patterns have defined meanings. Memory holds 128×12=1536 payload bits, equivalent to 192 eight-bit bytes if ideally packed, without specifying a physical storage layout.

Answer: The instruction is LOAD direct 13, encoded as decimal 269 or hexadecimal 0x10D. Successive states are (40,40,0), (43,40,0) and (43,40,43), with tuple order ACC, M[13], M[14]. The operand denotes address 13 because the opcode defines direct addressing. STORE direct 14 selects a different destination and therefore preserves M[13]. Capacity counts are 32 opcode patterns, 128 operand values and 4096 raw instruction patterns; the ideal packed memory payload is 1536 bits or 192 eight-bit bytes. These counts do not validate undefined opcodes or establish a byte-addressed physical memory.

Check your understanding: Restart from ACC=0, M[13]=40, M[14]=0, and instead run LOAD immediate 13; ADD direct 13; STORE direct 14. Give every state and explain the changed result. Then rerun both programs with M[13]=7. Finally, can the instruction LOAD direct 128 or opcode 11111 be accepted by silently shortening its bits or inventing an operation?

Answer: The changed program's states are (13,40,0), (53,40,0) and (53,40,53). LOAD immediate supplies the datum 13; ADD direct retrieves 40 from cell 13. With M[13]=7, the original program's states are (7,7,0), (10,7,0), (10,7,10), while the changed program gives (13,7,0), (20,7,0), (20,7,20). Both preserve the source cell and replace cell 14. Operand 128 is outside the unsigned seven-bit range, so LOAD direct 128 is rejected rather than truncated; zero would be a different address. Opcode 11111 is undefined and is rejected before executing or mutating state. No unspecified overflow or negative-value convention can make either rejected instruction valid.

Why: The useful diagnostic is to change the contents at an address while retaining the operand bits. A direct operand still names the same location but retrieves a different word; an immediate operand keeps supplying the same datum. The second program also moves the memory dependency from the load to the addition, which is why a complete trace explains more than a final number. Checking operand width and opcode definition before execution prevents an invalid pattern from being mistaken for an ordinary wrong calculation. Neither a larger accumulator nor the existence of spare opcode patterns expands the immediate field or defines a new operation.